In one conventional computing arrangement, a first network node transmits packets to and receives packets from a second network node via a network. The first node is a mobile computer that includes a battery to power the first node. In order to try to reduce the first node's power consumption, and thereby extend the first node's battery life, the first node implements a power utilization scheme in which its central processing unit (CPU) and/or network communication components are put into a reduced power state (e.g., relative to a fully powered up state) when the CPU and/or components are not actively in use processing packets received and/or to be transmitted via the network. When the first node receives a packet, one or more interrupts may be generated that may result in the CPU and/or these components being returned to a fully powered up state to permit the CPU and/or these components to process the received packet.
In operation, packets may be received by the first node according to a non-deterministic timing, thereby resulting in such interrupts being generated at a correspondingly non-deterministic timing. This may result in the first node's central processing unit and/or network communication components undergoing frequent, non-deterministically timed power state transitions. This may reduce the efficacy of the power utilization scheme in reducing the first node's power consumption. It may also reduce the first node's efficiency in processing certain types of packet traffic.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.